This application claims the benefit of Korean Patent Application No. 98-32891, filed Aug. 13, 1998, the disclosure of which is hereby incorporated herein by reference.
The present invention relates generally to the field of integrated circuit testing, and, more particularly, to integrated circuit devices having a built-in self-test (BIST) capability.
As the integration level of integrated circuit devices increases, traditional methods for device testing and verification may become obsolete. Devices may contain thousands of internal input/output (I/O) lines, but the number of I/O pins provided at the exterior of a device is typically limited by size and space constraints. Accordingly, testing techniques in which test patterns are applied to a device""s external inputs and the responses measured on the device""s external outputs may not be capable of thoroughly testing for internal defects in the device.
One technique that can be used to directly test the internal structures of a device is known as built-in self-test (BIST). Broadly stated, BIST involves the addition of test apparatus to a component, such as an integrated circuit device, a board, or a system, that can allow the component to test itself. In the case of an integrated circuit device, a goal of BIST is to move much of the test equipment functions into the device under test so that the complexity of the interface between the test equipment and the external I/O pins may be reduced.
Two components that may be used in BIST apparatus are pseudo-random pattern generators (PRPG) and multiple-input signature registers (MISR). Both PRPGs and MISRs typically comprise a linear feedback shift register (LFSR) as their core. The structure and operation of a conventional PRPG and a conventional MISR is described hereafter with reference to FIGS. 1 and 2 respectively.
With reference to FIG. 1, a conventional PRPG 10 comprises an LFSR that includes a plurality of coefficient blocks 11 , 12, 13, and 14, EXCLUSIVE-OR gates 15, 16, 17, and 18, and D flip-flops 19, 20, 21, and 22 that are connected as illustrated. As shown in FIG. 1, The D flip-flops 19, 20, 21, and 22 are configured in a serial arrangement such that the output from one flip-flop is connected to the input of another flip-flop through an EXCLUSIVE-OR gate 15, 16, 17, and 18. The output of each D flip-flop 19, 20, 21, and 22 is updated in response to a clock signal CLK. The coefficients 11, 12, 13, and 14 are used to selectively form feedback loops between the output of the last D flip-flop 22 in the series and each EXCLUSIVE-OR gate 15, 16, 17, and 18. When a coefficient is set to one, a feedback path is formed. Conversely, when a coefficient is set to zero, a feedback path is not formed. Thus, the LFSR of FIG. 1 includes a plurality of successive stages with each stage comprising a coefficient block, an EXCLUSIVE-OR gate, and a D flip-flop. During operation, the PRPG 10 generates an n-bit sequence of pseudo-random patterns at the outputs of the D flip-flops 19, 20, 21, and 22. The sequence is pseudo-random in the sense that the probability of a one or a zero is approximately fifty percent, but the sequence is repeatable.
An LFSR as shown in FIG. 1 can also be characterized as a primitive polynomial, P(X), as set forth in Equation 1 below:
P(X)=1+C1 X+C2X2+ . . . +Cnxe2x88x921Xnxe2x88x921+CnXnxe2x80x83xe2x80x83EQ. 1
where the coefficient blocks 11, 12, 13, and 14 correspond to the coefficients in the polynomial. The degree of the polynomial corresponds to the number of stages in the LFSR.
Referring now to FIG. 2, it is shown that a conventional MISR 30 may comprise a plurality of EXCLUSIVE-OR gates 31, 32, 33, and 34, D flip-flops 35, 36, 37, and 38, and coefficient blocks 39, 40, 41, and 42, that are connected as illustrated. The composition and operation of the MISR 30 shown in FIG. 2 is substantially the same as the PRPG/LFSR 10 discussed above with reference to FIG. 1. One difference, however, is that the EXCLUSIVE-OR gates 31, 32, 33, and 34 receive output data D1, D2, Dnxe2x88x92and Dn from, for example, a device under test. The output data D1-Dn are representative of a stream or sequence of output patterns generated by a device under test in response to the pseudo-random patterns generated by the PRPG 10 of FIG. 1. The MISR 30 compresses this entire stream or sequence of output patterns into a single signature value. The signature can then be compared with a desired value to determine whether the device under test is functioning properly. This determination can be made using internal decision circuitry or the signature could be made available outside of the testing apparatus (i.e., the PRPG 10 and the MISR 30) to another component where the test results are evaluated.
During a test session, it may be desirable to test various functional blocks in a device or circuit. In this regard, FIG. 3 shows a conventional test circuit for testing a plurality of functional blocks using a plurality of PRPGs/LFSRs 50, 51, 52, 53 and MISRs 54, 55, 56, 57. In the example shown, block A 58, block B 59, block C 60, and block D 61 denote different functional blocks in an integrated circuit under test. An LFSR-MISR pair is assigned to each block as illustrated. When a test is performed, pseudo-random patterns are generated by the LFSRs 50, 51, 52, and 53 under the supervision of a test control unit 62 and are provided to the functional blocks 58, 59, 60, and 61. In response, each functional block 58, 59, 60, and 61 generates a stream or sequence of output patterns, which are provided to the corresponding MISRs 54, 55, 56, and 57 to be compressed into signatures. The test control unit 62 then compares these signatures with expected values to determine if the functional blocks 58, 59, 60, and 61 are operating properly.
Unfortunately, as the number of functional blocks in an integrated circuit increases, the number of PRPGs/LFSRs and MISRs used to test these blocks generally increases at the same rate. As a result, the area needed on a chip to implement the test circuitry (i.e., PRPGs/LFSRs, MISRs) might become excessive.
It is therefore an object of the present invention to provide improved integrated circuit devices having a self-test capability.
It is another object of the present invention to allow layout area used for self-test apparatus in an integrated circuit device having a plurality to functional or test blocks to be reduced.
These and other objects, advantages, and features of the present invention may be provided by integrated circuit devices that have a self-test capability and methods of testing same in which a sequence of input data patterns are generated by a test pattern unit and are selectively applied to a functional or test block that is selected from a plurality of potential test blocks. The output data patterns that are generated by the selected test block are provided to a data compression unit that generates a signature in response thereto. This signature can then be compared with an expected pattern to determine whether the selected test block is functioning properly. Because the test pattern unit and the data compression unit are shared by a plurality of test blocks, the area normally reserved for test circuitry in an integrated circuit device can be reduced.
In accordance with an illustrative embodiment of the present invention, both the test pattern unit and the data compression unit are implemented using a single memory and a single polynomial block.
In accordance with another illustrative embodiment of the present invention, the test pattern unit and the data compression unit are implemented using distinct memories and polynomial blocks.
In accordance with still another illustrative embodiment of the present invention, multiple test units and data compression units can be used to facilitate the testing of integrated circuit devices in which the functional or test blocks do not have the same number of input ports. For example, a first test unit can be used to generate a sequence of n-bit data patterns to be applied to a selected first test block. The output data patterns that are generated by the selected first test block are provided to a first data compression unit that generates a first signature in response thereto. Similarly, a second test unit can be used to generate a sequence of m-bit data patterns to be applied to a second test block. The output data patterns that are generated by the selected second test block are provided to a second data compression unit that generates a second signature in response thereto. Thus, the functionality of test blocks having different numbers of input ports can be tested substantially simultaneously.
The built-in self-test apparatus according to the present invention can be implemented in a relatively small area on a chip because the self-test apparatus is shared by a plurality of functional or test blocks. Moreover, the built-in self-test apparatus can be applied to a printed circuit substrate or other large circuit as well as to the chip of a semiconductor integrated circuit.